1. Field of the Invention
The present invention relates to a semiconductor device having a structure in which signal pins are concentrated on one side of a package such as a Rambus DRAM (Dynamic Random Access Memory), etc.
2. Prior Art
A conventional semiconductor device of this kind will next be explained with reference to FIGS. 3A and 3B and 4.
FIGS. 3A and 3B are a view showing an SHP (Surface Horizontal Package) type Rambus DRAM. FIG. 3A is a side view of this SHP type Rambus DRAM and FIG. 3B is a plan view of this SHP type Rambus DRAM. FIG. 4 is a plan view showing a lead frame for the conventional SHP type DRAM and shows a state of the lead frame after a semiconductor chip is mounted to the lead frame and wire bonding is performed. In FIG. 4, only a forming portion of one semiconductor device is enlarged and drawn.
In FIGS. 3A and 3B, reference numeral 1 designates the conventional SHP type Rambus DRAM (hereinafter, simply called a semiconductor device). Reference numeral 2 designates seal resin for forming a package of this semiconductor device 1. In this semiconductor device 1, many pins 3 for external connection are projected in one side portion of the seal resin 2 and four pins 4 for support are projected in another side portion of the seal resin 2. The semiconductor device 1 is mounted onto the surface of an unillustrated printed wiring board by these pins. Only the above pins 3 for external connection among these pins are connected to a semiconductor chip described later within the seal resin 2.
A lead frame used to manufacture this semiconductor device 1 is formed as shown in FIG. 4. In FIG. 4, this lead frame is designated by reference numeral 5. This lead frame 5 is formed by two lead frame portions 6, 6 extending in a vertical direction in FIG. 4, tie bars 7, 8 for connecting these lead frame portions 6 to each other, an island 11 connected to these tie bars 7, 8 through supporting leads 9, 10, and many leads 12 for external connection extending from the tie bar 8 located on a lower side in FIG. 4 among the above tie bars 7, 8 to a side of the other tie bar 7. The semiconductor chip 13 is mounted to the above island 11. An electrode for a signal and an unillustrated electrode for a fixing potential (ground) on this semiconductor chip 13 are connected to an inner lead portion 12a of the above lead 12 for external connection by a bonding wire 14.
The above supporting lead 9 supports a center of the island 11 on its upper side. The above supporting lead 10 supports two island portions on both lower sides of the island 11. The supporting lead 9 and the supporting lead 10 are folded in their intermediate portions such that the island 11 is one-sided below the lead frame portion 6 and the tie bars 7, 8. These folding portions are designated by reference numerals 9a, 10a.
A basic end portion 10b of the above supporting lead 10 on a side of the tie bar 8, and an outer lead portion 12b of the lead 12 for external connection connected to the tie bar 8 form the pins 3 for external connection shown in FIG. 3. The pins 4 for support are formed integrally with the tie bar 7 and are not connected to the semiconductor chip 13.
When the semiconductor device 1 is manufactured by using this lead frame 5, the semiconductor chip 13 is mounted to the island 11 and wire bonding is performed as shown in FIG. 4. Thereafter, the seal resin 2 is first molded. This resin is sealed by mounting the lead frame 5 to a mold die of an unillustrated transfer molding machine and injecting the seal resin in a melting state into a cavity of this mold die and solidifying this seal resin. In this lead frame 5, a range sealed by the seal resin 2 is shown by a two-dotted chain line in FIG. 4.
After the resin seal process is terminated, a forming portion of the semiconductor device is separated from this lead frame 5. At this time, the outer lead portion 12b of the lead 12 for external connection, the basic end portion 10b of the supporting lead 10 and the pins 4 for support are set to be left on a side of the seal resin 2. Thereafter, the pins 3 for external connection and the pins 4 for support projected from the seal resin 2 onto its side are folded as shown in FIG. 3(a) so that a manufacture process of this semiconductor device 1 is terminated.
However, in this semiconductor device 1, there is a limit in an increase in an operating speed of the semiconductor chip 13. This is because no heat radiating property can be improved and no parasitic impedance of a signal system can be reduced.
The semiconductor device 1 of this kind, DRAMs, for example, Rambus, synchronous etc. attain an operating speed of several hundred MHz and a power assumption of several watts. Therefore, the semiconductor chip 13 is raised in temperature at an operating time of the semiconductor device. The semiconductor chip 13 of the semiconductor device 1 manufactured by using the lead frame shown in FIG. 4 is cooled by conducting lead through the supporting lead 10 and the seal resin 2 and externally radiating this heat. At this time, no electric current flows through the supporting lead 10. Accordingly, when the supporting lead 10 is soldered to a printed wiring board, the supporting lead 10 is not necessarily connected to a wiring pattern widely extending on the printed wiring board. Therefore, a ratio of heat conducted onto a side of the printed wiring board through the supporting lead 10 is extremely small so that the heat of this semiconductor device 1 is mainly radiated into the atmosphere through the seal resin 2. Namely, the heat must be radiated through the seal resin 2 having a low coefficient of thermal conductivity in comparison with a metal. Accordingly, no heat radiating property can be improved so that no semiconductor chip 13 can be operated at high speed.
Further, the lead 12 for external connection and the supporting lead 10 are connected to one tie bar 8 and the inner lead portion 12a must be arranged in a space except for the supporting lead 10 so that a degree of freedom is low in the designs of a shape and a size of the inner lead portion 12a. Namely, no signal system connected to an electrode of the semiconductor chip 13 can be formed in a mode for reducing parasitic impedance so that no operating speed of the semiconductor chip 13 can be increased.
To solve such disadvantages, for example, as disclosed in Japanese Patent Application Laid-Open No. 63-47351, it is considered that an electrode for a fixing potential of the semiconductor chip is connected to the supporting lead by a bonding wire and the function of a lead for a fixing potential is provided to this supporting lead. Namely, the supporting lead 10 is connected to a wiring pattern for a fixing potential of the printed wiring board by connecting the electrode for a fixing potential of the semiconductor chip 13 to the supporting lead 10 shown in FIG. 4 by the bonding wire. Accordingly, heat transmitted from the semiconductor chip 13 to the island 11 is radiated in a wide range of the printed wiring board so that the heat radiating property can be improved. Further, the lead 12 for external connection formed for the fixing potential and the supporting lead 10 can be constructed by one lead so that a space for extending the inner lead portion 12a is widened. Accordingly, a degree of freedom on design of the inner lead portion 12a is increased and the inner lead portion 12a can be formed such that parasitic impedance is reduced.
However, in the lead frame 5 shown in FIG. 4, two supporting leads 10 are connected to one side (one side on which the outer lead portion 12b is arranged in parallel) of the island 11. Accordingly, when the above structure is adopted, the heat of the semiconductor chip 13 is radiated from one side of the island 11 so that the heat radiating property is improved, but a thermal distribution of the operated semiconductor chip 13 is one-sided. It is considered that the number of supporting leads 10 is increased to uniform this thermal distribution. However, to do this, the island 11 must be constructed such that this island 11 can be supported by the supporting leads in well balance. This is because it is necessary that no island 11 is inclined by the seal resin when the seal resin in a melting state is injected into the mold die in the resin seal process. When the island 11 is inclined, there is a case in which the bonding wire 14 is pulled and disconnected and an upper side corner portion of the semiconductor chip 13 is exposed to a surface of the seal resin 2.